The present invention relates generally to integrated circuits (ICs), and more specifically, to a method for monitoring an input clock signal to an IC.
ICs generally include several logic elements. Some logic elements require clocking for their operation. These elements work synchronously with each other. The synchronous operation of the elements requires an accurate clocking system. Typically, an input clock signal is provided to the IC and distributed among the elements requiring clocking.
The input clock signal switches alternately between two logic levels, i.e. a low logic level and a high logic level, during correct operation. Failure of the input clock signal occurs when the input clock signal does not switch from one logic level to another or when the input clock signal becomes unavailable. The input clock signal is not able to switch between the logic levels if it gets stuck at a particular logic level. The elements of an IC can malfunction due to failure of the input clock signal. To avoid malfunctioning of these elements, clock monitor systems are provided to monitor the input clock signal. These clock monitor systems provide a signal indicating the failure of the input clock signal to the IC.
Most clock monitor systems monitor the input clock signal by comparing it with a reference clock signal. The reference clock signal is generated using either an on-chip ring oscillator circuit or an external clock generator circuit. To monitor an input clock signal having a frequency range between 8 MHz and 40 MHz, it is essential that the reference clock signal generated by a reference clock generator circuit is less than 8 MHz. It is very complex to design a ring oscillator circuit of frequency less than 8 MHz considering process, voltage and temperature variations in an IC. Further, some wireless chips operate at a low frequency of 32.768 KHz. Designing a low frequency ring oscillator circuit requires great effort and increases the size of the IC. Therefore, including a reference clock signal in an IC leads to increased design time, complexity and system cost.